Dynamic Random Access Memory utilizes capacitors to store bits of information within an integrated circuit. A capacitor is formed by placing a dielectric material between two electrodes formed from conductive materials. A capacitor's ability to hold electrical charge (i.e., capacitance) is a function of the surface area of the capacitor plates A, the distance between the capacitor plates d (i.e. the physical thickness of the dielectric layer), and the relative dielectric constant or k-value of the dielectric material. The capacitance is given by:
                    C        =                              κɛ            o                    ⁢                      A            d                                              (                  Eqn          .                                          ⁢          1                )            where ∈o represents the vacuum permittivity.
The dielectric constant is a measure of a material's polarizability. Therefore, the higher the dielectric constant of a material, the more electrical charge the capacitor can hold. Therefore, for a given desired capacitance, if the k-value of the dielectric is increased, the area of the capacitor can be decreased to maintain the same cell capacitance. Reducing the size of capacitors within the device is important for the miniaturization of integrated circuits. This allows the packing of millions (mega-bit (Mb)) or billions (giga-bit (Gb)) of memory cells into a single semiconductor device. The goal is to maintain a large cell capacitance (generally ˜10 to 25 fF) and a low leakage current (generally <10−7 A cm−2). The physical thickness of the dielectric layers in DRAM capacitors could not be reduced unlimitedly in order to avoid leakage current caused by tunneling mechanisms which exponentially increases as the thickness of the dielectric layer decreases.
Traditionally, SiO2 has been used as the dielectric material and semiconducting materials (semiconductor-insulator-semiconductor [SIS] cell designs) have been used as the electrodes. The cell capacitance was maintained by increasing the area of the capacitor using very complex capacitor morphologies while also decreasing the thickness of the SiO2 dielectric layer. Increases of the leakage current above the desired specifications have demanded the development of new capacitor geometries, new electrode materials, and new dielectric materials. Cell designs have migrated to metal-insulator-semiconductor (MIS) and now to metal-insulator-metal (MIM) cell designs for higher performance.
Typically, DRAM devices at technology nodes of 80 nm and below use MIM capacitors wherein the electrode materials are metals. These electrode materials generally have higher conductivities than the semiconductor electrode materials, higher work functions, exhibit improved stability over the semiconductor electrode materials, and exhibit reduced depletion effects. The electrode materials must have high conductivity to ensure fast device speeds. Representative examples of electrode materials for MIM capacitors are metals, conductive metal oxides, conductive metal silicides, conductive metal nitrides (i.e. TiN), or combinations thereof. MIM capacitors in these DRAM applications utilize insulating materials having a dielectric constant, or k-value, significantly higher than that of SiO2 (k=3.9). For DRAM capacitors, the goal is to utilize dielectric materials with k values greater than about 40. Such materials are generally classified as high-k materials. Representative examples of high-k materials for MIM capacitors are non-conducting metal oxides, non-conducting metal nitrides, non-conducting metal silicates or combinations thereof. These dielectrics may also include additional dopant materials.
One class of high-k dielectric materials possessing the characteristics required for implementation in advanced DRAM capacitors are high-k metal oxide materials. Titanium dioxide (TiO2) is a metal oxide dielectric material which displays significant promise in terms of serving as a high-k dielectric material for implementation in DRAM capacitors.
The dielectric constant of a dielectric material may be dependent upon the crystalline phase(s) of the material. For example, in the case of TiO2, the anatase crystalline phase of TiO2 has a dielectric constant of approximately 40, while the rutile crystalline phase of TiO2 can have a dielectric constant of approximately >80. Due to the higher-k value of the rutile-phase, it is desirable to produce TiO2 based DRAM capacitors with the TiO2 in the rutile-phase. The relative amounts of the anatase phase and the rutile phase can be determined from x-ray diffraction (XRD). From Eqn. 1 above, a TiO2 layer in the rutile-phase could be physically thicker and maintain the desired capacitance. The increased physical thickness is important for lowering the leakage current of the capacitor. The anatase phase will transition to the rutile phase at high temperatures (>800 C). However, high temperature processes are undesirable in the manufacture of DRAM devices.
The crystal phase of an underlying layer can be used to influence the growth of a specific crystal phase of a subsequent material if their crystal structures are similar and their lattice constants are similar. This technique is well known in technologies such as epitaxial growth. The same concepts have been extended to the growth of thin films where the underlying layer can be used as a “template” to encourage the growth of a desired phase over other competing crystal phases.
Generally, as the dielectric constant of a material increases, the band gap of the material decreases. This leads to high leakage current in the device. As a result, without the utilization of countervailing measures, capacitor stacks implementing high-k dielectric materials may experience large leakage currents. High work function electrodes (e.g., electrodes having a work function of greater than 5.0 eV) may be utilized in order to counter the effects of implementing a reduced band gap high-k dielectric layer within the DRAM capacitor. Metals, such as platinum, gold, ruthenium, and ruthenium oxide are examples of high work function electrode materials suitable for inhibiting device leakage in a DRAM capacitor having a high-k dielectric layer. The noble metal systems, however, are prohibitively expensive when employed in a mass production context. Moreover, electrodes fabricated from noble metals often suffer from poor manufacturing qualities, such as surface roughness, poor adhesion, and form a contamination risk in the fab.
Conductive metal oxides, conductive metal silicides, conductive metal nitrides, or combinations thereof comprise other classes of materials that may be suitable as DRAM capacitor electrodes. Generally, transition metals and their conductive binary compounds form good candidates as electrode materials. The transition metals exist in several oxidation states. Therefore, a wide variety of compounds are possible. Different compounds may have different crystal structures, electrical properties, etc. It is important to utilize the proper compound for the desired application.
In one example, molybdenum has several binary oxides of which MoO2 and MoO3 are two examples. These two oxides of molybdenum have different properties. MoO2 has shown great promise as an electrode material in DRAM capacitors. MoO2 has a distorted rutile crystal structure and serves as an acceptable template to promote the deposition of the rutile-phase of TiO2 as discussed above. MoO2 also has a high work function (can be >5.0 eV depending on process history) which helps to minimize the leakage current of the DRAM device. However, oxygen-rich phases (MoO2+x) degrade the performance of the MoO2 electrode because they do not promote the deposition of the rutile-phase of TiO2. For example, MoO3 (the most oxygen-rich phase) has an orthorhombic crystal structure.
Generally, a deposited thin film may be amorphous, crystalline, or a mixture thereof. Furthermore, several different crystalline phases may exist. Therefore, processes (both deposition and post-treatment) must be developed to maximize the formation of crystalline MoO2 and to minimize the presence of MoO2+x phases. Deposition processes and post-treatment processes in a reducing atmosphere have been developed that allow crystalline MoO2 to be used as the first electrode (i.e. bottom electrode) in MIM DRAM capacitors with TiO2 or doped-TiO2 high-k dielectric materials. Examples of the post-treatment process are further described in U.S. application Ser. No. 13/084,666 filed on Apr. 12, 2011, entitled “METHOD FOR FABRICATING A DRAM CAPACITOR” which is incorporated herein by reference. However, these MIM DRAM capacitors have continued to use noble metal (i.e. Ru) materials for the second electrode (i.e. top electrode).
The use of crystalline MoO2 as a second electrode in MIM DRAM capacitors has been difficult due to a number of problems. After the formation of the second electrode, the capacitor stack is then subjected to a post metallization anneal (PMA) treatment. The PMA treatment serves to crystallize the second electrode and to anneal defects and interface states that are formed at the dielectric/second electrode interface during the deposition. Also, if there is no post dielectric anneal (PDA) treatment done before metallization, PMA treatment can served to crystallize the dielectric layer. Examples of the PDA and PMA treatments are further described in U.S. application Ser. No. 13/159,842 filed on Jun. 14, 2011, entitled “METHOD OF PROCESSING MIM CAPACITORS TO REDUCE LEAKAGE CURRENT” and having internal docket number (IM0223_US) and is incorporated herein by reference. As discussed above, MoO2 is sensitive to oxidation to oxygen-rich compounds that negatively impact its performance as an electrode material. The reducing atmosphere anneal processes discussed previously with respect to the use of crystalline MoO2 as a first electrode are not an option at this stage of the device manufacture because they would degrade the performance of the dielectric layer through the formation of oxygen vacancies.
Additionally, DRAM capacitor stacks may undergo various refinement process steps after fabrication. These refinement processes may include post-fabrication chemical and thermal processing (i.e., oxidation or reduction). For instance, after initial DRAM capacitor stack fabrication, a number of high temperature (up to about 600 C) processes may be applied to complete the device fabrication. During these subsequent process steps, the DRAM electrode materials must remain chemically, physically, and structurally stable. They must maintain the structural, compositional, physical, and electrical properties that have been developed. Furthermore, they should not undergo significant interaction or reaction with the dielectric layer which may degrade the performance of the DRAM capacitor.
Therefore, there is a need to develop methods for the formation of non-noble metal materials for use as a second electrode in MIM DRAM capacitors that are compatible with PMA treatments and the remaining steps used to fabricate the DRAM device. Specifically, there is a need to develop methods for the formation of metal oxide materials for use as a second electrode in MIM DRAM capacitors that are compatible with PMA treatments and the remaining steps used to fabricate the DRAM device.